1. Field of the Invention
The present invention relates to computer systems using a core logic chipset to interface a central processor(s) (CPU), an AGP bus, input-output peripherals and random access memory together, and more particularly, in utilizing the same core logic circuits to provide a system area network interface through the AGP bus.
1. Description of the Related Technology
Use of computers, especially personal computers, in business and at home is becoming more and more pervasive because the computer has become an integral tool of most information workers who work in the fields of accounting, law, engineering, insurance, services, sales and the like. Rapid technological improvements in the field of computers have opened many new applications heretofore unavailable or too expensive for the use of older technology mainframe computers. These personal computers may be stand-alone workstations (high end individual personal computers), desk-top personal computers, portable lap-top computers and the like, or they may be linked together in a network by a "network server" which is also a personal computer which may have additional features specific to its purpose in the network. The network server may be used to store massive amounts of data, and may facilitate interaction of the individual workstations connected to the network for electronic mail ("E-mail"), document databases, video teleconferencing, whiteboarding, integrated enterprise calendar, virtual engineering design and the like. Multiple network servers may also be interconnected by local area networks ("LAN") and wide area networks ("WAN").
A computer system has a plurality of information (data and address) buses such as a host bus, a memory bus, high speed expansion buses such as an Accelerated Graphics Port (AGP) bus, a Peripheral Component Interconnect (PCI) bus, and other peripheral buses such as the Small Computer System Interface (SCSI), Extension to Industry Standard Architecture (EISA), and Industry Standard Architecture (ISA). The processor(s) of the computer system communicates with main memory and with the peripherals that make up the computer system over these various buses.
A significant part of the ever-increasing popularity of the personal computer, besides its low cost relative to just a few years ago, is its ability to run sophisticated programs and perform many useful and new tasks. Personal computers today may be easily upgraded with new peripheral devices for added flexibility and enhanced performance. A major advance in the performance of personal computers (both workstation and network servers) has been the implementation of sophisticated peripheral devices such as video graphics adapters, local area network interfaces, SCSI bus adapters, full motion video, redundant error checking and correcting disk arrays, and the like. These sophisticated peripheral devices are capable of data transfer rates approaching the native speed of the computer system's central processing unit ("CPU").
The peripheral devices' data transfer speeds are achieved by connecting the peripheral devices to the microprocessor(s) and associated system random access memory through high-speed expansion local buses. Most notably, a high speed expansion local bus standard has emerged that is microprocessor independent and has been embraced by a significant number of peripheral hardware manufacturers and software programmers. This high-speed expansion bus standard is called the "Peripheral Component Interconnect" or "PCI." A more complete definition of the PCI local bus may be found in the PCI Local Bus Specification, revision 2.1; PCI/PCI Bridge Specification, revision 1.0; PCI System Design Guide, revision 1.0; and PCI BIOS Specification, revision 2.1, the disclosures of which are hereby incorporated by reference for all purposes. These PCI specifications are available from the PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214.
A computer system has a plurality of information (data and address) buses such as a host bus, a memory bus, at least one high speed expansion local bus such as the PCI bus, and other peripheral buses such as the Small Computer System Interface (SCSI), Extension to Industry Standard Architecture (EISA), and Industry Standard Architecture (ISA). The microprocessor(s) of the computer system communicates with main memory and with the peripherals that make up the computer system over these various buses. The microprocessor(s) communicates to the main memory over a host bus to memory bus bridge. The peripherals, depending on their data transfer speed requirements, are connected to the various buses which are connected to the microprocessor host bus through bus bridges that detect required actions, arbitrate, and translate both data and addresses between the various buses.
Increasingly sophisticated microprocessors have revolutionized the role of the personal computer by enabling complex applications software to run at mainframe computer speeds. The latest microprocessors have brought the level of technical sophistication to personal computers that, just a few years ago, was available only in mainframe and minicomputer systems. Some representative examples of these new microprocessors are the "PENTIUM" and "PENTIUM PRO" (registered trademarks of Intel Corporation). Advanced Micro Devices, Digital Equipment Corporation, Cyrix, IBM and Motorola also manufacture advanced microprocessors.
These sophisticated microprocessors have, in turn, made possible running complex application programs using advanced three dimensional ("3-D") graphics for computer aided drafting and manufacturing, engineering simulations, games and the like. Increasingly complex 3-D graphics require higher speed access to ever-larger amounts of graphics data stored in memory. This memory may be part of the video graphics processor system, but, preferably, would be best (lowest cost) if part of the main computer system memory. Intel Corporation has proposed a low cost but improved 3-D graphics standard called the "Accelerated Graphics Port" (AGP) initiative. With AGP 3-D, graphics data, in particular textures, may be shifted out of the graphics controller local memory to computer system memory. The computer system memory is lower in cost than the graphics controller local memory and is more easily adapted for a multitude of other uses besides storing graphics data.
The proposed Intel AGP 3-D graphics standard defines a high-speed data pipeline, or "AGP bus," between the graphics controller and system memory. This AGP bus has sufficient bandwidth for the graphics controller to retrieve textures from system memory without materially affecting computer system performance for other non-graphics operations. The Intel 3-D graphics standard is a specification, which provides signal, protocol, electrical, and mechanical specifications for the AGP bus and devices attached thereto. This specification is entitled "Accelerated Graphics Port Interface Specification version 2.0," dated May 4, 1998; and also "Accelerated Graphics Port Interface Specification version 1.0," dated Jul. 31, 1996 are hereby incorporated by reference for all purposes. The AGP specification, both versions 2.0 and 1.0, are available from Intel Corporation, Santa Clara, Calif.
The AGP interface specification uses the 66 MHz PCI (Revision 2.1) as an operational baseline, with three performance enhancements to the PCI specification which are used to optimize the AGP specification for high performance 3-D graphics applications. These enhancements are: 1) pipelined memory read and write operations, 2) demultiplexing of address and data on the AGP bus by use of sideband signals, and 3) data transfer rates in excess of 500 megabytes per second ("MB/sec.") using the AGP 2x mode. The remaining AGP specification does not modify the PCI 2.1 specification, but rather provides a range of graphics-oriented performance enhancements for use by the 3-D graphics hardware and software designers. The AGP specification is neither meant to replace or diminish full use of the PCI standard in the computer system. The AGP specification creates an independent and additional high speed local bus for use by 3-D graphics devices such as a graphics controller, wherein the other input-output ("I/O") devices of the computer system may remain on any combination of the PCI, SCSI, EISA and ISA buses.
To functionally enable this AGP 3-D graphics bus, new computer system hardware and software are required. This requires new computer system core logic designed to function as a host bus/memory bus/PCI bus to AGP bus bridge meeting the AGP specification, and new Read Only Memory Basic Input Output System ("ROM BIOS") and Application Programming Interface ("API") software to make the AGP dependent hardware functional in the computer system. The computer system core logic must still meet the PCI standards referenced above and facilitate interfacing the PCI bus(es) to the remainder of the computer system. This adds additional costs to a personal computer system, but is well worth it if 3-D graphics are utilized. Some personal computer uses such as a network server do not require 3-D graphics, but would greatly benefit from having a second random access memory interface.
AGP capabilities are very desirable in a personal computer utilizing 3-D graphics, however, it is wasteful and redundant for those personal computers not requiring 3-D capabilities. The cost/performance (i.e., flexibility of the computer for a given price) of a personal computer is of paramount importance for commercial acceptance in the market place. In today's competitive computer industry, technical performance alone does not guarantee commercial success. Technical performance and flexibility of use for any personal computer product must be maximized while constantly reducing its manufacturing costs. To achieve a high performance to cost ratio, commonality of components and high volume of use are important factors. Thus, commonality of components such as logic circuits, printed circuit boards, microprocessors, computer boxes and power supplies, will drive the costs down for both workstations and servers. In addition, the high-end workstations and network servers would benefit if one generic model of a personal computer could be effectively used in either capacity. Further benefits in reducing costs may be realized by using common components in portable and desktop (consumer and low-end business) computers.
Many personal computers are linked to networks that include other personal computers as well as file, web and database servers and other peripheral devices such as printers. Some of these networks are arranged in a client/server configuration where key information and processing is accomplished on a special server computer for broadcast to the requesting client (personal computer) and/or other personal computers on the network. The client/server arrangement relieves the client computer from several tasks. Client/server technology allows either smaller, less capable clients to be used, or enables more capable clients to perform other tasks and thereby enhance the capability of the network as a whole. Use of more capable clients in a client server network creates a market for "excess computing capacity." This capacity was underutilized for many years. However, within the last several years, a new technology has emerged to take advantage of the excess client computing capacity. This technology is called a system area network.
A system area network (SAN) is a specialized network that enables a higher level of interaction between the client PC and the network. Software applications that run on a SAN can utilize the idle capacity on various client PCs on a network. The PCs that run a SAN software application are grouped together in a "cluster." A cluster is defined as a group of autonomous servers that work together as a single processing resource in an application environment. Autonomous means that the individual servers have everything they need to be stand-alone--including processors, memory, and operating system software. Applications and data can reside anywhere within the cluster, but to the user or client application, a cluster appears as a single system and can be managed as such.
One of the nagging problems of parallel processing is the approach to shared memory. Symmetric multiprocessor (SMP) systems run many commercial applications, yet they have certain scalability constraints. These constraints arise because SMP systems, regardless of the operating system, are shared-memory machines. When memory and other resources are shared among multiple processors, the addition of processors after a certain point (usually six to eight) results in resource contention. In addition, with a shared-memory architecture, the fault domain is spread across the entire system. This means that if there is a memory failure (hardware or software induced), the whole system fails, resulting in serious availability problems.
The use of a clustering architecture is an alternative to scaling up a shared-memory architecture system. Clustering architecture has its roots in fault-tolerant, massively parallel computing. Clustering architecture provides greatly enhanced scalability and reliability through the use of multiple, small-scale (low cost) SMP nodes (including uniprocessor nodes).
Viewed as a stack, a cluster can be broken into key elements, beginning with the hardware platform. On top of that resides the interconnection or I/O subsystem architecture. Residing on this physical layer are the software elements, starting with the operating system, followed by cluster-aware middleware (database, transaction processing, messaging, and other critical services). All of the above is topped with the application software.
All of the elements mentioned above must collaborate seamlessly to enable an efficient, scalable, reliable cluster. The middleware must shield programmers and users from the complexities of a multiprocessor environment, the interconnect technology must support the hardware architecture. Furthermore, the software and the hardware, working together, must support predictable scalability. Ultimately, however, a cluster will be only as good as its weakest link. For example, event the fastest hardware will not perform up to desired levels if the software is cluster efficient. Similarly, the cluster will "under perform" if there are significant bottlenecks, such as network connections of limited speed.
Many elements are involved in clustering, and there are many ways to build a cluster. However, there are two fundamental architectural models--shared-disk and shared-nothing. A shared-disk cluster design enables processors to share access to a disk storage subsystem. To exchange information in a shared-disk architecture, message are sent at high speed between groups of processors. Unlike the shared-disk architecture, the shared-nothing cluster provides processors with their own memory and I/O channels. The advantage of the shared-nothing architecture is that processors are not called upon to settle resource contention (or wait idly while a contention is resolved on their behalf by other devices). Even in a shared-nothing environment, however, there are still many demands on the cluster.
A major step in the evolution of clustering was the development of low-overhead, low latency system area networks that can scale to meet the most demanding throughput requirements. The interconnect technology is the "nerve system" of a cluster, tying together all of its various components--multiple server nodes, storage resources, and I/O devices. There are many possible cluster interconnect technologies--ethernet, asynchronous transfer mode (ATM), and other high-speed channels. Traditional LAN and WAN technologies, however, are often too slow to be suitable cluster interconnects. Faster versions of these technologies can contribute significantly to the overall performance of the cluster. Increased bandwidth for input-output ("I/O"), and their associated busses, would greatly facilitate the utilization of parallel applications on a SAN.
What is needed is an apparatus and system for a personal computer that may provide a network interface to a SAN by utilizing multiple-use high production volume logic and interface circuits having the capability of providing either the SAN interface or an AGP interface.